Title: Principal Physical Design Engineer
Locations: San Jose CA, or Irvine CA (onsite)
Package: 180-225k base, 30% bonus and huge stocks package! Total package around $400-700k!
Introduction
We are a global tech leader in the semiconductor industry. We have been supplying cutting edge networking ASIC's and multi-chip solutions for the past 30 years.
Top Reasons To Work With Us
Low stress environment with great work/life balance
Amazing package with base, strong bonus and industry leading RSU program!
Work for an industry leader in high growth mode with huge career growth potential
What You Will Be Doing
Are you an experienced engineer who excels at leading cross-functional teams, both internally and externally? Do your peers see you as an expert in physical design, STA, DFT, and packaging? Have you successfully taped out numerous chips, identifying and resolving potential design issues in EDA reports, advising design teams on fixes, and documenting your findings in application briefs? If this sounds like you and you're seeking a new challenge, we have an exciting opportunity.
We are seeking seasoned physical design engineers to lead teams in creating some of the most advanced chips in the industry, including those for AI, ML, HPC, and networking. In this critical role, you will represent our company to customers whose designs push the boundaries of technology.
Key Responsibilities:
Serve as the main point of contact between customers and internal engineering teams, fostering strong collaborative relationships.
Oversee external customer ASIC projects from start to finish, including RFQs, legal matters, technology and IP collateral, design, testing, packaging, fabrication, bring-up, and production.
Execute physical design workflows to ensure customer tape-in netlists meet stringent tape-out quality standards.
Provide expert advice to customers on EDA best practices, workflows, and design methodologies, and organize Q&A sessions with technology specialists.
Anticipate and plan for potential design risks, working proactively with cross-functional teams to implement risk mitigation strategies.
Efficiently organize, prioritize, and manage multiple tasks simultaneously.
Engage in discussions about chip designs with marketing, sales, legal, and regulatory compliance teams.
Collaborate with internal engineering teams, sharing your technical expertise on critical projects.
Stay updated on the latest developments in IPs, technology, and end-user applications, and motivate yourself to continuously learn.
What You Need For The Position
You should have very solid skills with at least 2 of the following:
Bonus points for:
Analyze PPA tradeoffs involved amongst various library components, and architectures.
Knowledgeable in low power design and power management.
Well versed in EDA tools for physical design verification and sign-off.
Programming in TCL, shell and scripting languages
Exposure to SERDES communications protocols.
Logic design, chip architecture, microarchitecture, Verilog RTL coding
Front-end logic design verification, DRC, logic synthesis
Knowledge of DFT methods including scan, boundary scan, memory BIST and test and
repair.
Education/experience
BSEE and 12+ yrs experience OR
MSEE and 10+
Benefits
Generous package including:
For this position you must be currently authorized to work in the United States. We do not sponsor for this position.
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